1. FIELD OF USE
This invention relates to data processing systems and More particularly to a pipeline system in which subsequent stages in the pipeline control previous stages.
2. DESCRIPTION OF THE PRIOR ART
It is well known that data processing systems include a memory for storing instructions and operands, and a processing unit for executing the instructions. The processing unit fetches the instructions from memory, generates an operand address and fetches the operand or operands from memory. The processing unit then executes the instruction and stores the resulting operand or operands back into memory at a specified location. The processing unit then fetches the next instruction.
Serial operation, particularly the need to access memory often, was a limitation on system throughput. Accordingly, caches were added to the system to improve performance. Initially, the cache stored both instructions and operands, but later designs included an instruction cache and a data cache.
About the same time, the data processing designs were implemented in a pipeline operation. Whereas, heretofore instructions were executed serially, that is the next instruction was fetched only after the execution of the previous instruction was completed, in new designs the instruction execution was pipelined. In the pipeline operation, the system is organized into number of stages, such as an instruction stage in which the instruction is fetched and analyzed, an address stage in which the operand address is developed, a memory or cache stage in which the operand is fetched, and an execution stage in which the instruction is completed. The instructions are placed serially into the pipeline. As soon as the instruction operation is completed in the instruction stage, the instruction is passed on to the address stage and the next instruction to be executed is fetched. Therefore, in the four stage system described, different portions of four instructions could be executed at the same time.
However, certain instructions have a long execution time or require intervention by another program before the instruction may be executed. These instructions cause the instruction stage to stall the pipeline until the execution of the instruction is completed. The instruction stage will then restart the pipeline. This approach requires extensive additional logic in the instruction stage with its subsequent reduction in throughput to analyze each instruction.
Accordingly, it is a primary object of the present inventor to provide a low cost high performance production line system.
It is yet another object of the present invention to provide less complex apparatus for restarting a stalled pipeline.
It is another object of the invention to provide means for a subsequent stage of the production line system to control an earlier stage to complete the execution of the instruction thereby enabling the production line to restart.